PLL Designer - Phase-Locked Loop Circuit Design Tool

Design Parameters

PLL Architecture

Reference Frequency (MHz)

Output Frequency Min (MHz)

Output Frequency Max (MHz)

Loop Bandwidth (kHz)

Phase Margin (degrees)

Automatically calculates divider ratios, loop filter component values (E-series), and verifies stability margins for your PLL design.

Divider Configuration

Reference Divider

R = 1

Feedback Divider

N = -

PFD Frequency

Loop Filter (2nd Order Passive)

C1 (Integration)

R1 (Zero)

C2 (Pole)

Performance Metrics

Phase Margin

Gain Margin

Bandwidth

Lock Time

Integrated Jitter

Overshoot

Block Diagram